View MBM29DL162TE-90TN_6776203.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-20880-3e fujitsu semiconductor data sheet flash memory cmos 16m (2m 8/1m 16) bit dual operation mbm29dl16xte/be 70/90 n features ? 0.23 m m process technology ? simultaneous read/write operations (dual bank) multiple devices available with different bank sizes (refer to mbm29dl16xte/be device bank divisions table in n general description) host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program (continued) n product line up n packages part no. mbm29dl16xte/be70 mbm29dl16xte/be90 address access time (max) 70 ns 90 ns ce access time (max) 70 ns 90 ns oe access time (max) 30 ns 35 ns power supply voltage 3.0 v + 0.6 v - 0.3 v 48-pin plastic tsop (1) (fpt-48p-m19) 48-pin plastic tsop (1) (fpt-48p-m20) 48-pin plastic fbga (bga-48p-m11) marking side marking side
mbm29dl16xte/be 70/90 2 (continued) ? single 3.0 v read, program, and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop(1) (package suffix: tn C normal bend type, tr C reversed bend type) 48-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance 70 ns maximum access time ? sector erase architecture eight 4k word and thirty one 32k word sectors in word mode eight 8k byte and thirty one 64k byte sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hiddenrom region 64k byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of boot sectors, regardless of sector group protection/unprotection status at v acc , increases program performance ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? program suspend/resume suspends the program operation to allow a read in another sector with in the same device ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. ? in accordance with cfi (c ommon f lash memory i nterface) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29dl16xte/be 70/90 3 n general description the mbm29dl16xte/be are a 16m-bit, 3.0 v-only flash memory organized as 2m bytes of 8 bits each or 1m words of 16 bits each. the mbm29dl16xte/be are offered in a 48-pin tsop(1) and 48-ball fbga package. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. mbm29dl16xte/be are organized into two banks, bank 1 and bank 2, which are considered to be two separate memory arrays for operations. it is the fujitsus standard 3 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. in the mbm29dl16xte/be, a new design concept is implemented, so called sliding bank architecture. under this concept, the mbm29dl16xte/be can be produced a series of devices with different bank 1/bank 2 size combinations; 0.5 mb/15.5 mb, 2 mb/14 mb, 4 mb/12 mb, 8 mb/8 mb. the standard mbm29dl16xte/be offer access times 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29dl16xte/be are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29dl16xte/be are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29dl16xte/be are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29dl16xte/be memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29dl16xte/be 70/90 4 mbm29dl16xte/be device bank divisions table device part number organization bank 1 bank 2 megabits sector sizes megabits sector sizes mbm29dl161te/be 8/ 16 0.5 mbit eight 8k byte/4k word 15.5 mbit thirty-one 64k byte/32k word mbm29dl162te/be 2 mbit eight 8k byte/4k word, three 64k byte/32k word 14 mbit twenty-eight 64k byte/32k word mbm29dl163te/be 4 mbit eight 8k byte/4k word, seven 64k byte/32k word 12 mbit twenty-four 64k byte/32k word mbm29dl164te/be 8 mbit eight 8k byte/4k word, fifteen 64k byte/32k word 8 mbit sixteen 64k byte/32k word
mbm29dl16xte/be 70/90 5 n pin assignments (continued) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. we reset n.c. wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 normal bend reverse bend tsop(1) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by wp/acc n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side) (marking side) (fpt-48p-m19) (fpt-48p-m20)
mbm29dl16xte/be 70/90 6 (continued) n pin descriptions pin name function pin name function a 19 to a 0 , a- 1 address input ry/by ready/busy output dq 15 to dq 0 data input/output byte selects 8-bit or 16-bit mode ce chip enable wp /acc hardware write protection/ program acceleration oe output enable v ss device ground we write enable v cc device power supply reset hardware reset pin/ temporary sector group unprotection n.c. no internal connection fbga (top view) a 13 a 12 a 14 a 15 a 16 byte a 9 a 8 a 10 a 11 dq 7 dq 14 we reset n.c. a 19 dq 5 dq 12 ry/by wp/acc a 18 n.c. dq 2 dq 10 a 7 a 17 a 6 a 8 dq 0 dq 8 a 3 a 4 a 2 a 1 a 0 ce dq 15 /a -1 v ss dq 13 dq 6 v cc dq 4 dq 11 dq 3 dq 9 dq 1 oe v ss (bga-48p-m11) h6 a3 b3 c3 d3 e3 f3 a2 b2 c2 d2 e2 f2 a1 b1 c1 d1 e1 f1 g3 h3 g2 h2 g1 h1 a6 b6 c6 d6 e6 f6 a5 b5 c5 d5 e5 f5 a4 b4 c4 d4 e4 f4 g5 h5 g6 g4 h4 marking side
mbm29dl16xte/be 70/90 7 n block diagram n logic symbol v ss v cc bank 2 address bank 1 address we ce a 19 to a 0 (a -1 ) oe byte wp/acc reset dq 15 to dq 0 ry/by state control & command register x-decoder x-decoder cell matrix (bank 2) cell matrix (bank 1) y-gating & data latch y-gating & data latch dq 15 to dq 0 status control 20 a 19 to a 0 we oe ce dq 15 to dq 0 16 or 8 byte wp/acc reset a -1 ry/by
mbm29dl16xte/be 70/90 8 n device bus operation mbm29dl16xte/be user bus operations table (byte = v ih ) legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes are accessed via a command register write sequence. see mbm29dl16xte/ be command definitions table. *2: refer to sector group protection in n functional description. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = + 2.7 v to + 3.6 v *5: also used for the extended sector group protection. mbm29dl16xte/be user bus operations table (byte = v il ) legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes are accessed via a command register write sequence. see mbm29dl16xte/ be command definitions table. *2: refer to sector group protection in n functional description. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = + 2.7 v to + 3.6 v *5: also used for the extended sector group protection. operation ce oe we a 0 a 1 a 6 a 9 dq 15 to dq 0 reset wp /acc auto-select manufacturer code* 1 llhlllv id code h x auto-select device code* 1 llhhllv id code h x read* 3 llha 0 a 1 a 6 a 9 d out hx standby hxxxxxx high-z h x output disable l h h x x x x high-z h x write (program/erase) l h l a 0 a 1 a 6 a 9 d in hx enable sector group protection* 2, * 4 lv id lhlv id xhx verify sector group protection* 2, * 4 llhlhlv id code h x temporary sector group unprotection* 5 xxxxxxx x v id x reset (hardware) / standby xxxxxxx high-z l x boot block sector write protection xxxxxxx x x l operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 7 to dq 0 reset wp /acc auto-select manufacturer code* 1 llh l lllv id code h x auto-select device code* 1 llh l hllv id code h x read* 3 llha -1 a 0 a 1 a 6 a 9 d out hx standby hxx x xxxx high-z h x output disable lhh x xxxx high-z h x write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in hx enable sector group protection* 2, * 4 lv id llhlv id xhx verify sector group protection* 2, * 4 llh l lhlv id code h x temporary sector group unprotection* 5 xxx x xxxx x v id x reset (hardware) / standby xxx x xxxx high-z l x boot block sector write protection xxx x xxxx x x l
mbm29dl16xte/be 70/90 9 mbm29dl16xte/be command definitions table command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* 1 word 1 xxxh f0h byte read/reset* 1 word 3 555h aah 2aah 55h 555h f0h ra* 7 rd* 7 byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h ia* 7 id* 7 byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah program suspend 1 bab0h program resume 1 ba30h chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 bab0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program* 2 word 2 xxxh a0h pa pd byte reset from fast mode* 2 word 2 ba 90h xxxh * 6 f0h byte extended sector group protection* 3 word 3 xxxh 60h spa 60h spa 40h spa* 7 sd* 7 byte query * 4 word 1 (ba) 55h 98h byte (ba) aah hiddenrom entry word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hiddenrom program* 5 word 4 555h aah 2aah 55h 555h a0h pa (hra) pd byte aaah 555h aaah hiddenrom erase* 5 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hiddenrom exit* 5 word 4 555h aah 2aah 55h (hrba) 555h 90hxxxh00h byte aaah 555h (hrba) aaah
mbm29dl16xte/be 70/90 10 notes: address bits a 19 to a 11 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). bus operations are defined in mbm29dl16xte/be user bus operations tables (byte = v ih and byte = v il ). ra: address of the memory location to be read ia : autoselect read address that sets both the bank address specified at (a 19 , a 18 , a 17 , a 16 , a 15 ) and all the other a 6 , a 1 , a 0 , (a -1 ). pa: address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa: address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba: bank address (a 19 to a 15 ) rd: data read from location ra during read operation. id : device code/manufacture code for the address located by ia. pd: data to be programmed at location pa. data is latched on the rising edge of write pulse. spa: sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd: sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra: address of the hiddenrom area 29dl16xte (top boot type) word mode: 0f8000h to 0fffffh byte mode: 1f0000h to 1fffffh 29dl16xbe (bottom boot type) word mode: 000000h to 007fffh byte mode: 000000h to 00ffffh hrba: bank address of the hiddenrom area 29dl16xte (top boot type) :a 19 = a 18 = a 17 = a 16 = a 15 = v ih 29dl16xbe (bottom boot type) :a 19 = a 18 = a 17 = a 16 = a 15 = v il the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 10 to a 0 byte mode: aaah or 555h to addresses a 10 to a 0 and a C1 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in command definitions table are illegal. *1: both of these reset commands are equivalent. *2: this command is valid during fast mode. *3: this command is valid while reset = v id (except during hiddenrom mode). *4: the valid addresses are a 6 to a 0 . *5: this command is valid during hiddenrom mode. *6: the data 00h is also acceptable. *7: the fourth bus cycle is only for read.
mbm29dl16xte/be 70/90 11 *1: a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3: when v id is applied to a 9 , both bank1 and bank2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. (b) : byte mode (w) : word mode hi-z : high-z *: at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. mbm29dl161te/be sector group protection verify autoselect codes table type a 19 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code byte ba* 3 v il v il v il v il 04h word x 0004h device code mbm29dl161te byte ba* 3 v il v il v ih v il 36h word x 2236h mbm29dl161be byte ba* 3 v il v il v ih v il 39h word x 2239h sector group protection byte sector group addresses v il v ih v il v il 01h* 2 word x 0001h* 2 extended autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code (b)* 04h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000100 (w) 0004h 00000000000 00100 device code mbm29dl161te (b)* 36h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00110110 (w)2236h00100010001 10110 mbm29dl161be (b)* 39h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00111001 (w)2239h00100010001 11001 sector group protection (b)* 01h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000001 (w) 0001h 0 0000000000 00001
mbm29dl16xte/be 70/90 12 *1 : a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. (b) : byte mode (w) : word mode hi-z : high-z * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. mbm29dl162te/be sector group protection verify autoselect codes table type a 19 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code byte ba* 3 v il v il v il v il 04h word x 0004h device code mbm29dl162te byte ba* 3 v il v il v ih v il 2dh word x 222dh mbm29dl162be byte ba* 3 v il v il v ih v il 2eh word x 222eh sector group protection byte sector group addresses v il v ih v il v il 01h* 2 word x 0001h* 2 extended autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code (b)* 04h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000100 (w)0004h00000000000 00100 device code mbm29dl162te (b)* 2dh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00101101 (w)222dh00100010001 01101 mbm29dl162be (b)* 2eh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00101110 (w)222eh00100010001 01110 sector group protection (b)* 01h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000001 (w)0001h00000000000 00001
mbm29dl16xte/be 70/90 13 *1 : a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. (b) : byte mode (w) : word mode hi-z : high-z * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. mbm29dl163te/be sector group protection verify autoselect codes table type a 19 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code byte ba* 3 v il v il v il v il 04h word x 0004h device code mbm29dl163te byte ba* 3 v il v il v ih v il 28h word x 2228h mbm29dl163be byte ba* 3 v il v il v ih v il 2bh word x 222bh sector group protection byte sector group addresses v il v ih v il v il 01h* 2 word x 0001h* 2 extended autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code (b)* 04h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000100 (w)0004h00000000 00000100 device code mbm29dl163te (b)* 28h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00101000 (w)2228h00100010 00101000 mbm29dl163be (b)* 2bh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00101011 (w) 222bh 0 0 100010 00101011 sector group protection (b)* 01h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 0000000 1 (w)0001h00000000 00000001
mbm29dl16xte/be 70/90 14 *1 : a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. (b) : byte mode (w) : word mode hi-z : high-z * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. mbm29dl164te/be sector group protection verify autoselect codes table type a 19 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code byte ba* 3 v il v il v il v il 04h word x 0004h device code mbm29dl164te byte ba* 3 v il v il v ih v il 33h word x 2233h mbm29dl164be byte ba* 3 v il v il v ih v il 35h word x 2235h sector group protection byte sector group addresses v il v ih v il v il 01h* 2 word x 0001h* 2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code (b)* 04h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000100 (w)0004h00000000 00000100 device code mbm29dl164te (b)* 33h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00110011 (w)2233h00100010 00110011 mbm29dl164be (b)* 35h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00110101 (w)2235h00100010 00110101 sector group protection (b)* 01h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 00000001 (w)0001h00000000 00000001
mbm29dl16xte/be 70/90 15 n flexible sector-erase architecture note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ) sector address table (mbm29dl161te) bank sector sector address sector size (kbytes/ kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 64/32 00 0000h to 00ffffh 000000h to 007fffh sa1 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa3 00011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa5 00101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa7 00111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa9 01001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1001010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1101011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1201100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1301101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1401110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa1501111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa1610000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa1710001xxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa1810010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa1910011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2010100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2110101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2210110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2310111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2411000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa2511001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa2611010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa2711011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa2811100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa2911101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3011110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh bank 1 sa3111111000 8/4 1f0000h to 1f1fffh0f 8000h to 0f8fffh sa3211111001 8/4 1f2000h to 1f3fffh0f 9000h to 0f9fffh sa3311111010 8/4 1f4000h to 1f5fffh0fa 000h to 0fafffh sa3411111011 8/4 1f6000h to 1f7fffh0fb 000h to 0fbfffh sa3511111100 8/4 1f8000h to 1f9fffh0fc 000h to 0fcfffh sa3611111101 8/4 1fa000h to 1fbfffh0fd 000h to 0fdfffh sa3711111110 8/4 1fc000h to 1fdfffh0fe 000h to 0fefffh sa3811111111 8/4 1fe0 00h to 1fffffh 0ff000h to 0fffffh
mbm29dl16xte/be 70/90 16 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl161be) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa3811111xxx 64/32 1f 0000h to 1fffffh 0f8000h to 0fffffh sa3711110xxx 64/321e 0000h to 1effffh 0f0000 to 0f7fffh sa3611101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3511100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa3411011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa3311010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa3211001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa3111000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa3010111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2910110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2810101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2710100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2610011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2510010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa24 1 0 0 0xxxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa2310000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa2201111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa2101110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa2001101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1901100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1801011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1701010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1601001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1501000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa1400111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa1300110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa1200101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa1100100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa1000011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa9 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa8 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh bank 1 sa7 00000111 8/4 00e0 00h to 00ffffh 007000h to 007fffh sa6 00000110 8/4 00c000h to 00dfffh00 6000h to 006fffh sa5 00000101 8/4 00a000h to 00bfffh00 5000h to 005fffh sa4 00000100 8/4 0 08000h to 009fffh 004000h to 004fffh sa3 00000011 8/4 0 06000h to 007fffh 003000h to 003fffh sa2 00000010 8/4 0 04000h to 005fffh 002000h to 002fffh sa1 00000001 8/4 0 02000h to 003fffh 001000h to 001fffh sa0 00000000 8/4 0 00000h to 001fffh 000000h to 000fffh
mbm29dl16xte/be 70/90 17 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ) sector address table (mbm29dl162te) bank sector sector address sector size (kbytes/ kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 64/32 00 0000h to 00ffffh 000000h to 007fffh sa1 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa3 00011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa5 00101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa7 00111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa9 01001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1001010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1101011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1201100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1301101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1401110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa1501111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa1610000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa1710001xxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa1810010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa1910011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2010100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2110101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2210110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2310111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2411000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa2511001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa2611010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa2711011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh bank 1 sa2811100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa2911101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3011110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3111111000 8/4 1f0000h to 1f1fffh0f 8000h to 0f8fffh sa3211111001 8/4 1f2000h to 1f3fffh0f 9000h to 0f9fffh sa3311111010 8/4 1f4000h to 1f5fffh0fa 000h to 0fafffh sa3411111011 8/4 1f6000h to 1f7fffh0fb 000h to 0fbfffh sa3511111100 8/4 1f8000h to 1f9fffh0fc 000h to 0fcfffh sa3611111101 8/4 1fa000h to 1fbfffh0fd 000h to 0fdfffh sa3711111110 8/4 1fc000h to 1fdfffh0fe 000h to 0fefffh sa3811111111 8/4 1fe0 00h to 1fffffh 0ff000h to 0fffffh
mbm29dl16xte/be 70/90 18 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl162be) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa3811111xxx 64/32 1f 0000h to 1fffffh 0f8000h to 0fffffh sa3711110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3611101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3511100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa3411011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa3311010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa3211001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa3111000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa3010111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2910110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2810101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2710100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2610011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2510010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa24 1 0 0 0xxxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa2310000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa2201111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa2101110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa2001101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1901100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1801011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1701010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1601001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1501000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa1400111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa1300110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa1200101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa1100100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh bank 1 sa1000011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa9 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa8 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa7 00000111 8/4 00e0 00h to 00ffffh 007000h to 007fffh sa6 00000110 8/4 00c000h to 00dfffh00 6000h to 006fffh sa5 00000101 8/4 00a000h to 00bfffh00 5000h to 005fffh sa4 00000100 8/4 0 08000h to 009fffh 004000h to 004fffh sa3 00000011 8/4 0 06000h to 007fffh 003000h to 003fffh sa2 00000010 8/4 0 04000h to 005fffh 002000h to 002fffh sa1 00000001 8/4 0 02000h to 003fffh 001000h to 001fffh sa0 00000000 8/4 0 00000h to 001fffh 000000h to 000fffh
mbm29dl16xte/be 70/90 19 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ) sector address table (mbm29dl163te) bank sector sector address sector size (kbytes/ kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 64/32 00 0000h to 00ffffh 000000h to 007fffh sa1 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa3 00011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa5 00101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa7 00111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa9 01001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1001010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1101011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1201100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1301101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1401110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa1501111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa1610000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa1710001xxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa1810010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa1910011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2010100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2110101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2210110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2310111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh bank 1 sa2411000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa2511001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa2611010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa2711011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa2811100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa2911101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3011110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3111111000 8/4 1f0000h to 1f1fffh0f 8000h to 0f8fffh sa3211111001 8/4 1f2000h to 1f3fffh0f 9000h to 0f9fffh sa3311111010 8/4 1f4000h to 1f5fffh0fa 000h to 0fafffh sa3411111011 8/4 1f6000h to 1f7fffh0fb 000h to 0fbfffh sa3511111100 8/4 1f8000h to 1f9fffh0fc 000h to 0fcfffh sa3611111101 8/4 1fa000h to 1fbfffh0fd 000h to 0fdfffh sa3711111110 8/4 1fc000h to 1fdfffh0fe 000h to 0fefffh sa3811111111 8/4 1fe0 00h to 1fffffh 0ff000h to 0fffffh
mbm29dl16xte/be 70/90 20 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl163be) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa3811111xxx 64/32 1f 0000h to 1fffffh 0f8000h to 0fffffh sa3711110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3611101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3511100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa3411011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa3311010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa3211001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa3111000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa3010111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2910110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2810101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2710100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2610011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2510010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa24 1 0 0 0xxxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa2310000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa2201111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa2101110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa2001101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1901100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1801011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1701010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1601001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1501000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh bank 1 sa1400111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa1300110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa1200101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa1100100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa1000011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa9 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa8 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa7 00000111 8/4 00e0 00h to 00ffffh 007000h to 007fffh sa6 00000110 8/4 00c000h to 00dfffh00 6000h to 006fffh sa5 00000101 8/4 00a000h to 00bfffh00 5000h to 005fffh sa4 00000100 8/4 0 08000h to 009fffh 004000h to 004fffh sa3 00000011 8/4 0 06000h to 007fffh 003000h to 003fffh sa2 00000010 8/4 0 04000h to 005fffh 002000h to 002fffh sa1 00000001 8/4 0 02000h to 003fffh 001000h to 001fffh sa0 00000000 8/4 0 00000h to 001fffh 000000h to 000fffh
mbm29dl16xte/be 70/90 21 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ) sector address table (mbm29dl164te) bank sector sector address sector size (kbytes/ kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 64/32 00 0000h to 00ffffh 000000h to 007fffh sa1 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa3 00011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa5 00101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa7 00111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa9 01001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1001010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1101011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1201100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1301101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1401110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa1501111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh bank 1 sa1610000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh sa1710001xxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa1810010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa1910011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2010100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2110101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2210110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2310111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2411000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa2511001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa2611010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa2711011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa2811100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa2911101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3011110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3111111000 8/4 1f0000h to 1f1fffh0f 8000h to 0f8fffh sa3211111001 8/4 1f2000h to 1f3fffh0f 9000h to 0f9fffh sa3311111010 8/4 1f4000h to 1f5fffh0fa 000h to 0fafffh sa3411111011 8/4 1f6000h to 1f7fffh0fb 000h to 0fbfffh sa3511111100 8/4 1f8000h to 1f9fffh0fc 000h to 0fcfffh sa3611111101 8/4 1fa000h to 1fbfffh0fd 000h to 0fdfffh sa3711111110 8/4 1fc000h to 1fdfffh0fe 000h to 0fefffh sa3811111111 8/4 1fe0 00h to 1fffffh 0ff000h to 0fffffh
mbm29dl16xte/be 70/90 22 note: the address range is a 19 : a -1 if in byte mode (byte = v il ). the address range is a 19 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl164be) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa3811111xxx 64/32 1f 0000h to 1fffffh 0f8000h to 0fffffh sa3711110xxx 64/321e 0000h to 1effffh 0f0000h to 0f7fffh sa3611101xxx 64/321d 0000h to 1dffffh 0e8000h to 0effffh sa3511100xxx 64/321c 0000h to 1cffffh 0e0000h to 0e7fffh sa3411011xxx 64/321b 0000h to 1bffffh 0d8000h to 0dffffh sa3311010xxx 64/321a 0000h to 1affffh 0d0000h to 0d7fffh sa3211001xxx 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa3111000xxx 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa3010111xxx 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa2910110xxx 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa2810101xxx 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa2710100xxx 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa2610011xxx 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa2510010xxx 64/32 12 0000h to 12ffffh 090000h to 097fffh sa24 1 0 0 0xxxx 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa2310000xxx 64/32 10 0000h to 10ffffh 080000h to 087fffh bank 1 sa2201111xxx 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa2101110xxx 64/320e 0000h to 0effffh 070000h to 077fffh sa2001101xxx 64/320d 0000h to 0dffffh 068000h to 06ffffh sa1901100xxx 64/320c 0000h to 0cffffh 060000h to 067fffh sa1801011xxx 64/320b 0000h to 0bffffh 058000h to 05ffffh sa1701010xxx 64/320a 0000h to 0affffh 050000h to 057fffh sa1601001xxx 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa1501000xxx 64/32 08 0000h to 08ffffh 040000h to 047fffh sa1400111xxx 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa1300110xxx 64/32 06 0000h to 06ffffh 030000h to 037fffh sa1200101xxx 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa1100100xxx 64/32 04 0000h to 04ffffh 020000h to 027fffh sa1000011xxx 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa9 00010xxx 64/32 02 0000h to 02ffffh 010000h to 017fffh sa8 00001xxx 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa7 00000111 8/4 00e0 00h to 00ffffh 007000h to 007fffh sa6 00000110 8/4 00c000h to 00dfffh00 6000h to 006fffh sa5 00000101 8/4 00a000h to 00bfffh00 5000h to 005fffh sa4 00000100 8/4 0 08000h to 009fffh 004000h to 004fffh sa3 00000011 8/4 0 06000h to 007fffh 003000h to 003fffh sa2 00000010 8/4 0 04000h to 005fffh 002000h to 002fffh sa1 00000001 8/4 0 02000h to 003fffh 001000h to 001fffh sa0 00000000 8/4 0 00000h to 001fffh 000000h to 000fffh
mbm29dl16xte/be 70/90 23 sector group addresses table (mbm29dl16xte) (top boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000xxx sa0 sga1 00001xxx sa1 to sa3 00010xxx 00011xxx sga2 0 0 1xxxxxsa4 to sa7 sga3 0 1 0 x x x x x sa8 to sa11 sga4 0 1 1 x x x x x sa12 to sa15 sga5 1 0 0 x x x x x sa16 to sa19 sga6 1 0 1 x x x x x sa20 to sa23 sga7 1 1 0 x x x x x sa24 to sa27 sga8 11100xxx sa28 to sa30 11101xxx 11110xxx sga9 11111000 sa31 sga1011111001 sa32 sga1111111010 sa33 sga1211111011 sa34 sga1311111100 sa35 sga1411111101 sa36 sga1511111110 sa37 sga1611111111 sa38
mbm29dl16xte/be 70/90 24 sector group addresses table (mbm29dl16xbe) (bottom boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000 sa0 sga1 00000001 sa1 sga2 00000010 sa2 sga3 00000011 sa3 sga4 00000100 sa4 sga5 00000101 sa5 sga6 00000110 sa6 sga7 00000111 sa7 sga8 00001xxx sa8 to sa10 00010xxx 00011xxx sga9 0 0 1 x x x x x sa11 to sa14 sga10 0 1 0 x x x x x sa15 to sa18 sga11 0 1 1 x x x x x sa19 to sa22 sga12 1 0 0 x x x x x sa23 to sa26 sga13 1 0 1 x x x x x sa27 to sa30 sga14 1 1 0 x x x x x sa31 to sa34 sga15 11100xxx sa35 to sa37 11101xxx 11110xxx sga16 1 1 1 1 1 x x x sa38
mbm29dl16xte/be 70/90 25 common flash memory interface code table description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 02h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1bh 0027h v cc max (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1ch 0036h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min size buffer write 2 n m s 20h 0000h typical timeout per individual sector erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical 23h 0005h max timeout for buffer write 2 n times typical 24h 0000h max timeout per individual sector erase 2 n times typical 25h 0004h max timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0015h flash device interface description 02h : 8/ 16 28h 29h 0002h 0000h max. number of bytes in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0002h erase block region 1 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h description a 6 to a 0 dq 15 to dq 0 erase block region 2 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 31h 32h 33h 34h 001eh 0000h 0000h 0001h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0032h address sensitive unlock 00h = required 45h 0000h erase suspend 02h = to read & write 46h 0002h sector protection 00h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotection 01h = supported 48h 0001h sector protection algorithm 49h 0004h number of sector for bank 2 00h = not supported 1fh = mbm29dl161te 1ch = mbm29dl162te 18h = mbm29dl163te 10h = mbm29dl164te 1fh = mbm29dl161be 1ch = mbm29dl162be 18h = mbm29dl163be 10h = mbm29dl164be 4ah 00xxh burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h v acc (acceleration) supply minimum dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4dh 0085h v acc (acceleration) supply maximum dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4eh 0095h boot type 02h = mbm29dl16xbe 03h = mbm29dl16xte 4fh 00xxh program suspend 01h = supported 50h 0001h
mbm29dl16xte/be 70/90 26 n functional description ? simultaneous operation mbm29dl16xte/be have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 19 to a 15 ) with zero latency. the mbm29dl161te/be have two banks which contain bank 1 (8kb 8 sectors) and bank 2 (64kb 31 sectors). the mbm29dl162te/be have two banks which contain bank 1 (8kb 8 sectors, 64kb 3 sectors) and bank 2 (64kb 28 sectors). the mbm29dl163te/be have two banks which contain bank 1 (8kb 8 sectors, 64kb 7 sectors) and bank 2 (64kb 24 sectors). the mbm29dl164te/be have two banks which contain bank 1 (8kb 8 sectors, 64kb 15 sectors) and bank 2 (64kb 16 sectors). the simultaneous operation can not execute multi-function mode in the same bank. simultaneous operation table shows combination to be possible for simultaneous operation. (refer to (8) bank-to-bank read/write timing diagram in n timing diagram.) *: by writing erase suspend command on the bank address of sector being erased, the erase operation becomes suspended so that it enables reading from or programming the remaining sectors. ?read mode the mbm29dl16xte/be have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h to l. simultaneous operation table case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29dl16xte/be 70/90 27 ? standby mode there are two ways to implement the standby mode on the mbm29dl16xte/be devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. ? automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29dl16xte/be data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29dl16xte/be automatically switch themselves to low power mode when mbm29dl16xte/be addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29dl16xte/be read-out the data for changed addresses. ? output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. ? autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 6 , a 1 a 0 , and (a -1 ). (see mbm29dl16xte/be user bus operations ta b l e s ( b y t e = v ih and byte = v il ) in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29dl16xte/be are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29dl16xte/be command definitions table in n device bus operation. (refer to autoselect command in n command definitions.) word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code (mbm29dl161te = 36h and mbm29dl161be = 39h for 8 mode; mbm29dl161te = 2236h and mbm29dl161be = 2239h for 16 mode), (mbm29dl162te = 2dh and mbm29dl162be = 2eh for 8 mode; mbm29dl162te = 222dh and mbm29dl162be = 222eh for 16 mode), (mbm29dl163te = 28h and mbm29dl163be = 2bh for 8 mode; mbm29dl163te = 2228h and mbm29dl163be = 222bh for 16 mode),
mbm29dl16xte/be 70/90 28 (mbm29dl164te = 33h and mbm29dl164be = 35h for 8 mode; mbm29dl164te = 2233h and mbm29dl164be = 2235h for 16 mode). these two bytes/words are given in mbm29dl16xte/be sector group protection verify autoselect codes tables and expanded autoselect code tables in n device bus operation. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29dl16xte/be sector group protection verify autoselect codes tables and expanded autoselect code ta b l e s i n n device bus operation.) in case of applying v id on a 9 , since both bank 1 and bank 2 enter autoselect mode, the simultenous operation cannot be executed. ?write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac characteristics in n electrical characteristics and n timing diagram. ? sector group protection the mbm29dl16xte/be feature hardware sector group protection. this feature will disable both program and erase operations in any combination of 17 sector groups of memory. (see sector group addresses tables (mbm29dl16xte/be) in n flexible sector-erase architecture). the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il and a 0 = a 6 = v il , a 1 = v ih . the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address tables (mbm29dl161te/be, mbm29dl162te/be, mbm29dl163te/be, mbm29dl164te/be) in n flexible sector-erase architecture define the sector address for each of the thirty nine (39) individual sectors, and sector group addresses tables (mbm29dl16xte/be) in n flexible sector-erase architecture define the sector group address for each of the seventeen (17) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see (15) ac waveforms for sector group protection in n timing diagram and (5) sector group protection algorithm in n flow chart for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 6 , a 1 , and a 0 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector
mbm29dl16xte/be 70/90 29 group. see mbm29dl16xte/be sector group protection verify autoselect codes tables and expanded autoselect code tables in n device bus operation for autoselect codes. ? temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the mbm29dl16xte/be devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to (16) temporary sector group unprotection timing diagram in n timing diagram and (6) temporary sector group protection algorithm in n flow chart. ? reset hardware reset the mbm29dl16xte/be devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see (11) reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector group unprotection for additional functionality. ? byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29dl16xte/be devices. when this pin is driven high, the devices operate in the word (16-bit) mode.the data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 14 to dq 8 bits are tri-stated. refer to (12) timing diagram for word mode configuration, (13) timing diagram for byte mode configuration and (14) byte timing diagram for write operations in n timing diagram. ? boot block sector protection the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8k byte boot sectors (mbm29dl16xte: sa37 and sa38, mbm29dl16xbe: sa0 and sa1) independently of whether those sectors were protected or unprotected using the method described in sector group protection. the two outermost 8k byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. that is, sector group protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sector group protection.
mbm29dl16xte/be 70/90 30 ? accelerated program operation mbm29dl16xte/be offer accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fact program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see (18) accelerated program timing diagram in n timing diagram. erase operation at acceleration mode is strictly prohibited.
mbm29dl16xte/be 70/90 31 n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. some commands are required bank address (ba) input. when command sequences are inputed to bank being read, the commands have priority than reading. mbm29dl16xte/be command definitions ta b l e i n n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. ? read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to 2. ac characteristics read only operations characteristics in n electrical characteristics and n timing diagram. ? autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle from address (ba)01h for 16((ba)02h for 8) returns the device code (mbm29dl161te = 36h and mbm29dl161be = 39h for 8 mode; mbm29dl161te = 2236h and mbm29dl161be = 2239h for 16 mode), (mbm29dl162te = 2dh and mbm29dl162be = 2eh for 8 mode; mbm29dl162te = 222dh and mbm29dl162be = 222eh for 16 mode), (mbm29dl163te = 28h and mbm29dl163be = 2bh for 8 mode; mbm29dl163te = 2228h and mbm29dl163be = 222bh for 16 mode), (mbm29dl164te = 33h and mbm29dl164be = 35h for 8 mode; mbm29dl164te = 2233h and mbm29dl164be = 2235h for 16 mode). (see mbm29dl16xte/be sector group protection verify autoselect codes tables and expanded autoselect code tables in n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address (ba)02h for 16 ((ba)04h for 8). scanning the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see mbm29dl16xte/be user bus operations tables (byte = v ih and byte = v il ) in n device bus operation.)
mbm29dl16xte/be 70/90 32 the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector group protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. ? byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see hardware sequence flags table.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. (1) embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. ? program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address.writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming.the program suspend command mav also be issued during a programming operation while an erase is suspend.the bank addresses of sector being programed should be set when writing the program suspend command. when the program suspend command is written during a programming process , the device halts the program operation within 1 m s and updates the status bits. after the program operation has been suspended, the system can read data from any address.the data at program-suspend address is not valid. normal read timing and command definitions apply.
mbm29dl16xte/be 70/90 33 after the program resume command (30 h) is written, the device reverts to programming. the bank addresses of sector being suspended should be set when writing the program resume command. the system can determine the status of the program operation using the dq 7 or dq 6 status bits, just as in the standard program operation.see write operation status for more information. the system may also write the autoselect command sequence when the device in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. seeautoselect command for more information. the system must write the program resume command (address bits are bank address) to exit the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. ?chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) (2) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. ? sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29dl16xte/be command definitions table in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector.
mbm29dl16xte/be 70/90 34 in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. (2) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. ? erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erasing or suspending should be set when writting the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/by output pin will be at high-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended.
mbm29dl16xte/be 70/90 35 to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. ? extended command (1) fast mode mbm29dl16xte/be have fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to (7) embedded program tm algorithm for fast mode in n flow chart.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to (7) embedded program tm algorithm for fast mode in n flow chart.) (3) extended sector group protection in addition to normal sector group protection, the mbm29dl16xte/be have extended sector group protection as extended function. this function enables to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the extended sector group protection requires v id on reset pin only. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins), and write extended sector group protection command (60h). a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to (17) extended sector group protection timing diagram in n timing diagram and (8) extended sector group protection algorithm in n flow chart.) (4) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward- compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 in word mode (16 bit) read. refer to common flash memory interface code table in n flexble sector- erase architecture. to terminate operation, it is necessary to write the read/reset command sequence into the register. (see common flash memory interface code table in n flexible sector-erase architecture.)
mbm29dl16xte/be 70/90 36 ? hiddenrom region the hiddenrom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 64 kbytes in length and is stored at the same address of the 8 kb 8 sectors. the mbm29dl16xte occupies the address of the byte mode 1f0000h to 1fffffh (word mode 0f8000h to 0fffffh) and the mbm29dl16xbe type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh). after the system has written the enter hiddenrom command sequence, the system may read the hiddenrom region by using the addresses normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. ? hiddenrom entry command mbm29dl16xte/be have a hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it is protected. however, once it is protected, it is impossible to unprotect, so please use this with caution. hiddenrom area is 64 kbyte and in the same address area of 8 kb sectors. the address of top boot is 1f0000h to 1fffffh at byte mode (0f8000h to 0fffffh at word mode) and the bottom boot is 000000h to 00ffffh at byte mode (000000h to 007fffh at word mode). these areas are normally the boot block area (8 kb 8 sectors). therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. it is called as hiddenrom mode when the hiddenrom area appears. sector other than the boot block area could be read during hiddenrom mode. read/program/earse of the hiddenrom area is possible during hiddenrom mode. write the hiddenrom reset command sequence to exit the hiddenrom mode. the bank address of the hiddenrom should be set on the third cycle of this reset command sequence. in case of mbm29dl161te/be, whose bank 1 size is 0.5 mbit, the simultaneous operation cannot execute multi-function mode between the hiddenrom area and bank 2 region. ? hiddenrom program command to program the data to the hiddenrom area, write the hiddenrom program command sequence during hiddenrom mode. this command is the same as the program command in the past except to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the address to be programmed. if the address other than the hiddenrom area is selected to program, the data of the address will be changed. ? hiddenrom erase command to erase the hiddenrom area, write the hiddenrom erase command sequence during hiddenrom mode. this command is the same as the sector erase command in the past except to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the sector address to be erased. if the sector address other than the hiddenrom area is selected, the data of the sector will be changed.
mbm29dl16xte/be 70/90 37 ? hiddenrom protect command there are two methods to protect the hiddenrom area. one is to write the sector group protect setup command (60h), set the sector address in the hiddenrom area and (a 6 , a 1 , a 0 ) = (0,1,0), and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence could be used because except that it is in the hiddenrom mode and that it does not apply high voltage to reset pin, it is the same as the extension sector group protect in the past. please refer to extended command (3) extended sector group protection for details of extention sector group protect setting. the other is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 1 , a 0 ) = (0,1,0), and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 1 , a 0 ) = (0,1,0) and the sector address in the hiddenrom area, and read. when 1 appears to dq 0 , the protect setting is completed. 0 will appear to dq 0 if it is not protected. please apply write pulse agian. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same as the sector group protect in the past. please refer to sector group protection in n functional description for details of sector group protect setting other sector group will be effected if the address other than the hiddenrom area is selected for the sector group address, so please be carefull. once it is protected, protection can not be cancelled, so please pay closest attention. ? write operation status detailed in hardware sequence flags table are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank where is not operate embedded algorithm returns a data of memory cell. these bits offer a method for determining whether a embedded algorithm is completed properly. information on dq 2 is address sensitive. this means that if an address from an erasing sector is consectively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non- erasing sector is consectively read. this allows the user to determine which sectors are erasing and which are not. the status flag is not output from bank (non-busy bank) not executing embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cell is outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted.
mbm29dl16xte/be 70/90 38 *1 : successive reads from the erasing or erase-suspend sector cause dq 2 to toggle. *2 : reading from non-erase suspend sector address indicates logic 1 at the dq 2 bit. ?dq 7 data polling the mbm29dl16xte/be devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in (3) data polling algorithm in n flow chart. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the mbm29dl16xte/be data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are hardware sequence flags table status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* 1 erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1 * 2 program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29dl16xte/be 70/90 39 driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table.) see (6) ac waveforms for data polling during embedded algorithm operations in n timing diagram for the data polling timing specifications and diagrams. ?dq 6 toggle bit i the mbm29dl16xte/be also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (ce or oe toggling) data from the devices will result in dq 6 toggling between 1 and 0. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erasing or is erase-suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during the erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see (7) ac waveforms for toggle bit i during embedded algorithm operations in n timing diagram for the toggle bit i timing specifications and diagrams. ?dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in mbm29dl16xte/be user bus operations tables (byte = v ih and byte = v il ) in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the
mbm29dl16xte/be 70/90 40 dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. ?dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table. ?dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also toggle bit status table and (9) dq 2 vs. dq 6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. ? reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase
mbm29dl16xte/be 70/90 41 operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the begining of the algorithm when it returns to determine the status of the operation. (refer to (4) toggle bit algorithm in n flow chart.) toggle bit status table *1 : successive reads from the erasing or erase-suspend sector cause dq 2 to toggle. *2 : reading from the non-erase suspend sector address indicates logic 1 at the dq 2 bit. ?ry/by ready/busy the mbm29dl16xte/be provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/ write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands. if the mbm29dl16xte/be are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to (10) ry/by timing diagram during program/erase operations and (11) reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, the pull-up resistor needs to be connected to v cc ; multiples of devices may be connected to the host system via more than one ry/by pin in parallel. ? data protection the mbm29dl16xte/be are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle* 1 erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1* 2
mbm29dl16xte/be 70/90 42 ?low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min). if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. ? write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. ? logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logic 0 while oe is a logic 1. ? power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. ? sector group protection device user is able to protect each sector group individually to store and protect data. protection circuit voids both program and erase commands that are addressed to protected sectors. any command to program or erase addressed to protected sector are ignored (see sector group protection in n functional description).
mbm29dl16xte/be 70/90 43 n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe and reset pins is C0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in Cv cc ) does not exceed 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *4 : minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except a 9 , oe , reset * 1, * 2 v in , v out C0.5 v cc +0.5 v power supply voltage * 1 v cc C0.5 +4.0 v a 9 , oe , and reset * 1, * 3 v in C0.5 +13.0 v wp /acc * 1, * 4 v acc C0.5 +10.5 v parameter symbol conditions value unit min max ambient temperature t a mbm29dl16xte/be70/90 C40 +85 c power supply voltage* v cc mbm29dl16xte/be70/90 +2.7 +3.6 v
mbm29dl16xte/be 70/90 44 n maximum overshoot/maximum undershoot +0.6 v ?.5 v 20 ns ?.0 v 20 ns 20 ns maximum undershoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns note: this waveform is applied for a 9 , oe, and reset. maximum overshoot waveform 2
mbm29dl16xte/be 70/90 45 n electrical characteristics 1. dc characteristics (continued) parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 +1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v +35 m a wp /acc accelerated program current i lia v cc = v cc max, wp /acc = v acc max 20ma v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 5 mhz byte 13 ma word 15 ce = v il , oe = v ih , f = 1 mhz byte 7 ma word 7 v cc active current * 2 i cc2 ce = v il , oe = v ih 35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v, wp /acc = v cc 0.3 v 1 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v 1 5 m a v cc current (automatic sleep mode) * 5 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 1 5a v cc active current * 6 (read-while-program) i cc6 ce = v il , oe = v ih byte 48 ma word 50 v cc active current * 6 (read-while-erase) i cc7 ce = v il , oe = v ih byte 48 ma word 50 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih 35ma input low voltage v il C0.5+0.6v input high voltage v ih 2.0v cc +0.3 v voltage for autoselect and sector group protection (a 9 , oe , reset ) * 3, * 4 v id 11.5 12 12.5 v voltage for wp /acc sector group protection/unprotection and program acceleration * 4 v acc 8.59.09.5v output low voltage v ol i ol = 4.0 ma, v cc = v cc min 0.45 v output high voltage v oh1 i oh = C2.0 ma, v cc = v cc min 2.4 v v oh2 i oh = C100 m a v cc C 0.4 v low v cc lock-out voltage v lko 2.32.42.5v
mbm29dl16xte/be 70/90 46 (continued) *1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : this timing is only for sector group protection operation and autoselect mode. *4 : applicable for only v cc . *5 : automatic sleep mode enables the low power mode when address remains stable for 150 ns. *6 : embedded algorithm (program or erase) is in progress. (@5 mhz)
mbm29dl16xte/be 70/90 47 2. ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29dl16xte/be70) 1 ttl gate and 100 pf (mbm29dl16xte/be90) input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbol condi- tions 70 90 unit jedec standard min max min max read cycle time t avav t rc 70 ? 90 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 70 ? 90 ns chip enable to output delay t elqv t ce oe = v il ? 70 ? 90 ns output enable to output delay t glqv t oe ? 30 ? 35 ns chip enable to output high-z t ehqz t df ? 25 ? 30 ns output enable to output high-z t ghqz t df ? 25 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 0 ? 0 ? ns reset pin low to read mode t ready ? 20 ? 20 m s ce to byte switching low or high t elfl t elfh ? 5 ? 5ns c l 3.3 v diode = 1n3064 or equivalent 2.7 k w device under test diode = 1n3064 or equivalent 6.2 k w test conditions note : c l = 30 pf including jig capacitance (mbm29dl16xte/be70) c l = 100 pf including jig capacitance (mbm29dl16xte/be90)
mbm29dl16xte/be 70/90 48 ? write/erase/program operations (continued) parameter symbol 70 90 unit jedec standard min typ max min typ max write cycle time t avav t wc 70 ?? 90 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling t aso 12 ?? 15 ?? ns address hold time t wlax t ah 45 ?? 45 ?? ns address hold time from ce or oe high during toggle bit polling t aht 0 ?? 0 ?? ns data setup time t dvwh t ds 30 ?? 35 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable hold time read t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns ce high during toggle bit polling t ceph 20 ?? 20 ?? ns oe high during toggle bit polling t oeph 20 ?? 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 35 ?? ns ce pulse width t eleh t cp 35 ?? 35 ?? ns write pulse width high t whwl t wph 25 ?? 30 ?? ns ce pulse width high t ehel t cph 25 ?? 30 ?? ns programming operation byte t whwh1 t whwh1 ? 8 ?? 8 ? s word ? 16 ?? 16 ? s sector erase operation* 1 t whwh2 t whwh2 ? 1 ?? 1 ? s v cc setup time t vcs 50 ?? 50 ?? s rise time to v id * 2 t vidr 500 ?? 500 ?? ns rise time to v acc * 3 t vaccr 500 ?? 500 ?? ns voltage transition time* 2 t vlht 4 ?? 4 ?? s write pulse width* 2 t wpp 100 ?? 100 ?? s oe setup time to we active* 2 t oesp 4 ?? 4 ?? s ce setup time to we active * 2 t csp 4 ?? 4 ?? s recover time from ry/by t rb 0 ?? 0 ?? ns
mbm29dl16xte/be 70/90 49 (continued) *1 : this does not include preprogramming time. *2 : this timing is for sector group protection operation. *3 : this timing is limited for accelerated protection operation. n erase and programming performance parameter symbol 70 90 unit jedec standard min typ max min typ max reset pulse width t rp 500 ?? 500 ?? ns reset high level period before read t rh 200 ?? 200 ?? ns byte switching low to output high-z t flqz ?? 25 ?? 30 ns byte switching high to output active t fhqv ?? 70 ?? 90 ns program/erase valid to ry/by delay t busy ?? 90 ?? 90 ns delay time from embedded output enable t eoe ?? 70 ?? 90 ns erase time-out time t tow ?? 50 ?? 50 s erase suspend transition time t spd ?? 20 ?? 20 s parameter value unit comments min typ max sector erase time 1 10 s excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead byte programming time 8 300 m s chip programming time 50 s excludes system-level overhead program/erase cycle 100,000 cycle
mbm29dl16xte/be 70/90 50 n pin capacitance 1. tsop(1) pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. 2. fbga pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. parameter symbol condition value unit min typ max input capacitance c in v in = 0 ? 6.0 7.5 pf output capacitance c out v out = 0 ? 8.5 12.0 pf control pin capacitance c in2 v in = 0 ? 8.0 10.0 pf wp /acc pin capacitance c in3 v in = 0 ? 17.0 18.0 pf parameter symbol condition value unit min typ max input capacitance c in v in = = = = 0 ? 7.0 9.0 pf output capacitance c out v out = = = = 0 ? 9.5 13.0 pf control pin capacitance c in2 v in = = = = 0 ? 9.0 11.0 pf wp /acc pin capacitance c in3 v in = = = = 0 ? 17.0 18.0 pf
mbm29dl16xte/be 70/90 51 n timing diagram ? key to switching waveforms (1) ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oe outputs t rc address address stable high-z output valid high-z t oeh t oh
mbm29dl16xte/be 70/90 52 (2) ac waveforms for hardware reset/read operations (3) ac waveforms for alternate we controlled program operations reset t acc t oh outputs t rc address address stable high-z output valid t rh ce t rp t rh t ce t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. these address differ from 8 mode.
mbm29dl16xte/be 70/90 53 (4) ac waveforms for alternate ce controlled program operations t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. these address differ from 8 mode.
mbm29dl16xte/be 70/90 54 (5) ac waveforms for chip/sector erase operations v cc ce oe address data t wp we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h 10h for chip erase * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase. note : these waveforms are for the 16 mode. the addresses differ from 8 mode.
mbm29dl16xte/be 70/90 55 (6) ac waveforms for data polling during embedded algorithm operations t oeh t oe t whwh1 or t whwh2 ce oe t eoe t busy we data t df t ch t ce high-z high-z dq 7 = valid data dq 6 to dq 0 valid data dq 7 * dq 7 dq 6 to dq 0 ry/by data dq 6 to dq 0 = output flag * : dq 7 = valid data (the device has completed the embedded operation).
mbm29dl16xte/be 70/90 56 (7) ac waveforms for toggle bit i during embedded algorithm operations t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph * : dq 6 stops toggling (the device has completed the embedded operation).
mbm29dl16xte/be 70/90 57 (8) bank-to-bank read/write timing diagram (9) dq 2 vs. dq 6 ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note: this is the example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address corresponding to bank 1. ba2: address corresponding to bank 2. dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce * : dq 2 is read from the erase-suspended sector.
mbm29dl16xte/be 70/90 58 (10) ry/by timing diagram during program/erase operations (11) reset , ry/by timing diagram (12) timing diagram for word mode configuration rising edge of the last write pulse ce ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb dq 15 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) byte ce dq 14 to dq 0 dq 15 /a -1 t elfh t fhqv t ce a -1
mbm29dl16xte/be 70/90 59 (13) timing diagram for byte mode configuration (14) byte timing diagram for write operations ce byte dq 14 to dq 0 dq 15 /a -1 t elfl t acc t flqz dq 15 a -1 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) falling edge of the last write signal ce or we t ah t as input valid byte
mbm29dl16xte/be 70/90 60 (15) ac waveforms for sector group protection spax : sector group address to be protected spay : next sector group address to be protected note: a -1 is v il on byte mode. t vlht spax a 19 , a 18 , a 17 a 16 , a 15 , a 14 a 13 , a 12 spay a 6 , a 0 a 9 v ih t vlht oe v ih t vlht t vlht t oesp t wpp we ce t oe 01h data v cc a 1 t vcs v id v id t csp
mbm29dl16xte/be 70/90 61 (16) temporary sector group unprotection timing diagram v ih reset v cc ce we ry/by t vlht program or erase command sequence t vlht t vcs t vidr v id t vlht unprotection period
mbm29dl16xte/be 70/90 62 (17) extended sector group protection timing diagram spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 m s (min) note : a -1 is v il on byte mode. spay reset oe we ce data a 1 v cc a 6 , a 0 address spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc v id
mbm29dl16xte/be 70/90 63 (18) accelerated program timing diagram v ih wp/acc v cc ce we ry/by t vlht program command sequence t vlht t vcs t vaccr v acc t vlht acceleration period
mbm29dl16xte/be 70/90 64 n flow chart (1) embedded program tm algorithm no yes program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling increment address last address ? program address/program data start programming completed no verify data ? embedded program algorithm in program yes embedded algorithms notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl16xte/be 70/90 65 (2) embedded erase tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequence (see below) data polling chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start no data = ffh ? embedded program algorithm in program yes embedded algorithms notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl16xte/be 70/90 66 (3) data polling algorithm dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. = any of the sector addresses within the sector not being protected during chip erase operation.
mbm29dl16xte/be 70/90 67 (4) toggle bit algorithm no dq 6 = toggle ? dq 5 = 1? yes no yes read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start yes dq 6 = toggle ? no program/erase operation complete program/erase operation not complete. write reset command read dq 7 to dq 0 addr. = va *1 *1, *2 read dq 7 to dq 0 addr. = va *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changing to 1. va = bank address being executed embedded algorithm.
mbm29dl16xte/be 70/90 68 (5) sector group protection algorithm setup sector group addr. (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , ce = v il , reset = v ih a 6 = a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector group (addr. = spa, a 1 = v ih , a 6 = v 0 = v il ) * remove v id from a 9 write reset command increment plscnt no yes protect another sector group ? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector group protection completed * : a -1 is v il on byte mode.
mbm29dl16xte/be 70/90 69 (6) temporary sector group unprotection algorithm reset = v id * 1 perform erase or program operations reset = v ih start temporary sector group unprotection completed* 2 *1 : all protected sector groups are unprotected. *2 : all previously protected sector groups are protected once again.
mbm29dl16xte/be 70/90 70 (7) extended sector group protection algorithm device failed plscnt = 25 ? yes yes yes no no plscnt = 1 data = 01h? protection other sector group? sector group protection completed time out 250 m s reset = v id start wait to 4 m s to setup sector group protection write xxxh/60h extended sector group protection entry? increment plscnt no yes no read from sector group address (addr. = spa, a 6 = a 0 = v il , a 1 = v ih ) to verify sector group protection write 40h to sector address (a 6 = a 0 = v il , a 1 = v ih ) to sector group protection write 60h to sector address (a 6 = a 0 = v il , a 1 = v ih ) device is operating in temporary sector group unprotection mode remove v id from reset write reset command remove v id from reset write reset command setup next sector group address
mbm29dl16xte/be 70/90 71 (8) embedded program tm algorithm for fast mode no no yes yes 555h/20h xxxh/a0h verify data ? (ba)xxxh/90h xxxh/f0h programming completed last address ? data polling 2aah/55h set fast mode in fast program reset fast mode 555h/aah start program address/program data increment address fast mode algorithm notes: the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl16xte/be 70/90 72 n ordering information part no. package access tome remarks mbm29dl161te-70tn mbm29dl161te-90tn 48-pin plastic tsop (1) (fpt-48p-m19) normal bend 70 90 top sector mbm29dl162te-70tn MBM29DL162TE-90TN 70 90 mbm29dl163te-70tn mbm29dl163te-90tn 70 90 mbm29dl164te-70tn mbm29dl164te-90tn 70 90 mbm29dl161te-70tr mbm29dl161te-90tr 48-pin plastic tsop (1) (fpt-48p-m20) reverse bend 70 90 mbm29dl162te-70tr mbm29dl162te-90tr 70 90 mbm29dl163te-70tr mbm29dl163te-90tr 70 90 mbm29dl164te-70tr mbm29dl164te-90tr 70 90 mbm29dl161te-70pbt mbm29dl161te-90pbt 48-pin plastic fbga (bga-48p-m11) 70 90 mbm29dl162te-70pbt mbm29dl162te-90pbt 70 90 mbm29dl163te-70pbt mbm29dl163te-90pbt 70 90 mbm29dl164te-70pbt mbm29dl164te-90pbt 70 90 mbm29dl161be-70tn mbm29dl161be-90tn 48-pin plastic tsop (1) (fpt-48p-m19) normal bend 70 90 bottom sector mbm29dl162be-70tn mbm29dl162be-90tn 70 90 mbm29dl163be-70tn mbm29dl163be-90tn 70 90 mbm29dl164be-70tn mbm29dl164be-90tn 70 90 mbm29dl161be-70tr mbm29dl161be-90tr 48-pin plastic tsop (1) (fpt-48p-m20) reverse bend 70 90 mbm29dl162be-70tr mbm29dl162be-90tr 70 90 mbm29dl163be-70tr mbm29dl163be-90tr 70 90 mbm29dl164be-70tr mbm29dl164be-90tr 70 90 mbm29dl161be-70pbt mbm29dl161be-90pbt 48-pin plastic fbga (bga-48p-m11) 70 90 mbm29dl162be-70pbt mbm29dl162be-90pbt 70 90 mbm29dl163be-70pbt mbm29dl163be-90pbt 70 90 mbm29dl164be-70pbt mbm29dl164be-90pbt 70 90
mbm29dl16xte/be 70/90 73 mbm29dl16x t e 70 tn device number/description mbm29dl16x 16 mega-bit (2 m 8-bit or 1 m 16-bit) cmos flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e tn = 48-pin thin small outline package (tsop) standard pinout tr = 48-pin thin small outline package (tsop) reverse pinout pbt = 48-ball fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
mbm29dl16xte/be 70/90 74 n package dimensions (continued) 48-pin plastic tsop(1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. 48-pin plastic tsop(1) (fpt-48p-m20) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * * dimensions in mm (inches). note : the values in parentheses are reference values. C .003 +.001 .007 C 0.08 +0.03 0.17 "a" (stand off height) (.004 .002) 0.10 0.05 0.10(.004) (mounting height) 12.00 0.20(.472 .008) lead no. 48 25 24 1 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48030s-c-6-7 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part * * 0.50(.020) dimensions in mm (inches). note : the values in parentheses are reference values.
mbm29dl16xte/be 70/90 75 (continued) c 2001 fujitsu limited b48011s-c-5-3 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ (5.60(.220)) (4.00(.157)) 48-?.45 0.10 (48-?018 .004) m ?.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 .004 +.006 0.10 +0.15 1.05 dimensions in mm (inches). note : the values in parentheses are reference values. 48-pin plastic fbga (bga-48p-m11)
mbm29dl16xte/be 70/90 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0305 ? fujitsu limited printed in japan

▲Up To Search▲

Price & Availability of MBM29DL162TE-90TN

	To Download MBM29DL162TE-90TN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .